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1991 data sheet mos integrated circuit pd6376 audio 2-channel 16-bit d/a converter the pd6376 is an audio 2-channel 16-bit d/a converter. the pd6376 has low sound quality deterioration by employing the resistor string configuration and 0-point offset, and low power consumption by using the cmos process. it operates on a single 5-v power supply, and it is pin- compatible with the pd6372 when pin 1 is low level or open. features single 5-v power supply cmos structure on-chip output operational amplifier circuit on-chip 0-point offset circuit resistor string configuration ? f s (2 ch 400 khz) supported on-chip 2-channel dac l-r in-phase output ordering information part number package pd6376gs 16-pin plastic sop 7.62 mm (300) the mark shows major revised points. document no. s12799ej6v0ds00 (6th edition) date published june 2002 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
pd6376 2 data sheet s12799ej6v0ds block diagram 13 14 15 16 1 2 3451278 9 6 11 10 lrck/wdck lrsel/rsi si/lsi clk d.gnd nc a.gnd r.ref r.out l.out l.ref analog power supply block digital power supply block main dac main dac sub dac shift register latch timing generator sub dac d.v dd a.v dd 4/8 f s sel
pd6376 3 data sheet s12799ej6v0ds pin configuration (top view) 16-pin plastic sop 7.62 mm (300) 1 2 3 4 5 6 7 8 clk si/lsi lrsel/rsi lrck/wdck a.gnd l.out l.ref r.ref 16 15 14 13 12 11 10 9 4/8 f s sel d.gnd nc d.v dd a.gnd r.out a.v dd a.v dd
pd6376 4 data sheet s12799ej6v0ds 1. pin functions pin no. symbol name i/o function 1 4/8 f s sel input when this pin is low or leaves open, l-ch data and r-ch data is input in time-division from pin 15. when this pin is high, l-ch data is input from pin 15, and r-ch data is input from pin 14. (pulled down in ic with 100-k ? resistor) 2 d.gnd digital gnd gnd pin of logic block 3 nc non connection not connected to internal chip 4 d.v dd digital v dd power supply pin to logic block 5 a.gnd analog gnd gnd pin to analog block 6 r.out r-ch output output right analog signal output pin 7 a.v dd analog v dd power supply pin to analog block 8 a.v dd analog v dd 9 r.ref r-ch voltage reference reference voltage pin. normally connected to a. gnd 10 l.ref l-ch voltage reference through via capacitor to lower impedance 11 l.out l-ch output output left analog signal output pin 12 a.gnd analog gnd gnd pin of analog block 13 lrck/wdck left/right clock input when pin 1 is low or leaves open: word clock functions as l-r judgment signal input pin. when pin 1 is high: functions as input data word judgment signal input pin. 14 lrsel/rsi left/right selection input when pin 1 is low or leaves open: r-ch series input functions as pin to select l-r polarity for lrck signal. when lrck signal is high, set lrsel pin to low to input l-ch data; when lrck signal is low, set lrsel pin to high to input l-ch data. when pin 1 is high: functions as r-ch serial data input pin. 15 si/lsi series input input when pin 1 is low or open: l-ch series input functions as l-ch and r-ch serial data input pin alternately. when pin 1 is high: functions as l-ch serial data input pin. 16 clk clock input input pin for read clock of serial input data
pd6376 5 data sheet s12799ej6v0ds 2. input signal format input data must be input as 2? complement, msb first. 2? complement is a method of expressing both positive numbers and negative numbers as binary numbers. see the table below. 2? complement decimal number l.out, r.out pin voltage typ. (v) (msb) (lsb) (reference values) note 0111 1111 1111 1111 +32767 2.6 0111 1111 1111 1110 +32766 0000 0000 0000 0001 +1 0000 0000 0000 0000 0 1.6 1111 1111 1111 1111 ? 1000 0000 0000 0001 ?2767 1000 0000 0000 0000 ?2768 0.6 note when a.v dd = 5.0 v values differ depending on ic fabrication variations, supply voltage fluctuations, and ambient temperature. synchronize the (si, lsi, rsi) data bit delimitations and the lrck, wdck reverse timing to the falling edge of clk. clk requires the input of 16 clocks between sample data (16 bits). also, make the time interval for 1 bit the same as 1 clock cycle.
pd6376 6 data sheet s12799ej6v0ds 2.1 supplying clock to clk even outside sample data interval 2.1.1 serial data input (pin 1 is low or open) synchronize the reverse timing of lrck with the falling edge of clk upon completion of lsb input (point a in figure 2-1 ). figure 2-1 timing chart for serial data input a a interval of 1 sample data lsb clk si lrck 16 1234 1234 5678910111213141516 msb lsb msb 2.1.2. inputting parallel data (pin 1 is high) synchronize the timing of the falling edge of wdck with the falling edge of clk upon completion of lsb input of data (lsi, rsi) (point a in figure 2-2 .). figure 2-2 parallel data input timing chart a a lsb clk lsi rsi wdck 16 1234 12 5678910111213141516 msb lsb msb lsb 16 1234 12 5678910111213141516 msb lsb msb
pd6376 7 data sheet s12799ej6v0ds 2.2 supplying clock to clk only during sample data interval the analog outputs of the l.out and r.out pins are updated after the input of 4.5 clocks following data input. (see 4. electrical characteristics, timing charts 1 and 2 .) 2.2.1 inputting serial data (pin 1 low or open) place the lrck reverse timing between the falling edge of clk at lsb input completion (point a in figure 2-3 ) and the next msb input start time (point b in figure 2-3 ) (so as to include points a and b). figure 2-3 timing chart of serial data input a ab b 1-sample data interval lrck reverse interval lrck reverse interval lsb clk si lrck 16 1234 1234 5678910111213141516 msb lsb msb 2.2.2 inputting parallel data (pin 1 high) place the wdck falling edge timing between the falling edge of clk at lsb input completion (point a in figure 2-4 ) and the next msb input start time (point b in figure 2-4 ) (so as to include points a and b). place the wdck rising edge timing between the third falling edge of clk from msb input completion (point c in figure 2-4 ) and the falling edge of clk upon lsb input start (point d in figure 2-4 ) (so as to include points c and d). figure 2-4 timing chart of parallel data input a ab bc d wdck falling edge interval wdck falling edge interval wdck rising edge interval lsb clk lsi rsi wdck 16 1234 12 5678910111213141516 msb lsb msb lsb 16 1234 12 5678910111213141516 msb lsb msb
pd6376 8 data sheet s12799ej6v0ds 3. usage cautions insertion of a muting circuit in the next stage after the pd6376 is recommended. if no muting circuit is inserted in the next stage, shock noise may be generated when power is applied. remarks 1. the practical value is 1.6 0.2 v (when a.v dd = 5.0 v) for the dc offset at the l.out and r.out pins (dc voltage value when the input data is 0000h (hexadecimal number)). 2. there is no minimum value for the conversion frequency. the pd6376 can operate even when one sample data is input. 3. the minimum value of the full scale output voltage is a practical value of 1.7 v p-p .
pd6376 9 data sheet s12799ej6v0ds 4. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol rating unit supply voltage v dd 0.3 to +7.0 v output pin voltage v out 0.3 to v dd +0.3 v logic input voltage v in 0.3 to v dd +0.3 v operating ambient temperature t a 20 to +75 c storage temperature t stg 40 to +125 c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the device reliability may be impaired. the absolute maximum ratings are values that may physically damage the product. be sure to use the product within the ratings. recommended operating range parameter symbol condition min. typ. max. unit supply voltage v dd 4.5 5.0 5.5 v logic input voltage (high) v ih 0.7v dd v dd v logic input voltage (low) v il 0 0.3v dd v operating temperature range t a 20 +25 +75 c output load resistance r l r.out or l.out pin 5 k ? conversion frequency f s 400 khz clock frequency f clk 10 mhz clock pulse width f sck 40 ns si, lrck set time t dc 12 ns si, lrck hold time t cd 12 ns electrical characteristics (t a = 25 c, v dd = +5 v) parameter symbol condition min. typ. max. unit resolution res 16 bit total harmonic distortion 1 thd 1 f in = 1 khz, 0 db 0.04 0.09 % total harmonic distortion 2 thd 2 f in = 1 khz, 20 db 0.1 0.3 % full-scale output voltage v fs 1.7 2.0 2.3 v p-p cross talk c.t 0 db per channel, f in = 1 khz 85 95 db s/n ratio s/n jis-a 96 db dynamic range d.r f in = 1 khz, 60 db 92 db circuit current i dd f in = 1 khz, 0 db 6.0 12 ma
pd6376 10 data sheet s12799ej6v0ds timing chart 1 when pin 1 is low or open (serial input) 4.5 clocks lsb clk si lrck lrck l.out r.out 16 1 2345678910111213141516 msb lsb n note n 1 234567891011 msb (r-ch) (r-ch) (l-ch) (l-ch) n 1 n 1 analog output update note when the lrck signal is high, set the lrsel pin to low to input l-ch data. when the lrck signal is low, set the lrsel pin to h igh to input l-ch data. t sck t sck clk si t cd t dc clk lrck t dc t cd
pd6376 11 data sheet s12799ej6v0ds timing chart 2 when pin 1 is high (parallel input) t sck t sck clk si t cd t dc clk wdck t dc t cd 4.5 clocks lsb clk lsi rsi wdck l.out r.out 16 1 2345678910111213141516 msb lsb n 1 234567891011 msb n 1n lsb 16 1 2345678910111213141516 msb lsb n n + 1 1 234567891011 msb n 1n analog output update
pd6376 12 data sheet s12799ej6v0ds typical characteristics (t a = 25 c) note 20 khz low-pass filter: 298blr-010n (toko) used thd vs. frequency characteristics thd vs. v dd characteristics 1.0 0.5 0.3 0.2 0.1 0.05 0.03 0.02 0.01 0.1 0.2 0.3 0.5 1 frequency f (khz) ( 20 db) note f s = 88.2 khz v dd = 5.0 v note f s = 88.2 khz f in = 1 khz, 0 db (full scale) thd (%) 23 5 10 20 voltage gain vs. frequency characteristics 0 5 10 0.1 0.2 0.3 0.5 1 frequency f (khz) note f s = 88.2 khz v dd = 5.0 v voltage gain (db) 23 5 10 20 thd vs. r l characteristics 10 1.0 0.1 0.01 100 1 k 10 k 100 k load resistance r l ( ? ) note f s = 88.2 khz f in = 1 khz, 0 db v dd = 5.0 v thd (%) 1 m 1.0 0.5 0.3 0.2 0.1 0.05 0.03 0.02 0.01 0 3.0 4.0 5.0 6.0 7.0 v dd (v) thd (%) thd vs. v out characteristics note f s = 88.2 khz f in = 1 khz v dd = 5.0 v 10.0 5.0 3.0 2.0 1.0 0.5 0.3 0.2 0.1 0.05 0.03 0.02 0.01 60 50 40 30 20 10 0 v out (db) thd (%)
pd6376 13 data sheet s12799ej6v0ds 5. application circuit example (1) f s to 4 f s mode (l/r data serial input mode) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 123 456 78 16 15 14 13 12 11 10 9 384 f s lrck si clk +5 v +5 v +5 v +5 v +5 v +5 v +10 v +10 v op amp. op amp. note +5 v + + + + + + + 0.1 f 0.1 f 47 f ? 47 f 10 f 1/2 2/2 22 f 22 f l-ch out r-ch out 100 k ? 100 k ? 100 k ? 100 k ? 5.6 k ? 5.6 k ? 5.6 k ? 5.6 k ? 5.6 k ? 5.6 k ? 5.6 k ? 5.6 k ? + 10 f 1000 pf 1000 pf 1000 pf 1000 pf npc sm5807 pd6376gs note assuming secondary active lpf (gain: k = 2, quality factor: q = 1, cutoff frequency: f c . = . 30 khz) oversampling, the attenuation characteristics are moderate. if oversampling is not performed, use a high-order filter. remark operational amplifier (op amp.): pc4558 (2) 8 f s mode (l/r data parallel input mode) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 384 f s lrck si clk +5 v +5 v +5 v +5 v +10 v +10 v note +5 v +5 v + + + + + + + 0.1 f 0.1 f 47 f 47 f 10 f 22 f 22 f l-ch out r-ch out 100 k ? 100 k ? 100 k ? 100 k ? 5.6 k ? 5.6 k ? 5.6 k ? 5.6 k ? 5.6 k ? 5.6 k ? 5.6 k ? 5.6 k ? + 10 f 1000 pf 1000 pf 1000 pf 1000 pf npc sm5813 9 16 15 14 13 12 11 10 12345678 pd6376gs op amp. 1/2 op amp. 2/2 note secondary active lpf (k = 2, q = 1, f c . = . 30 khz) remark operational amplifier (op amp.): pc4558
pd6376 14 data sheet s12799ej6v0ds 6. measuring circuit example +5 v + + + 47 f 47 f 47 f 100 f 100 f 100 f 0.1 f 0.1 f + + + + 2/2 op amp. 2/2 5.6 k ? 5.6 k ? 5.6 k ? 3.6 k ? 3.6 k ? 5.6 k ? v dd pd6376 sampling frequency f s = 88.2 khz 3.6 k ? 3.6 k ? 100 k ? 200 ? l r 100 f + 100 k ? 200 ? + anritsu mg22a lrck 98 7 6 5 4 3 2 1 10 11 12 13 14 15 16 si clk lpf lpf v ref 298blr-010n (toko) 298blr-010n (toko) (+2.5 v) h.p. 339 a (30 khz lpf on) op amp. 1/2
pd6376 15 data sheet s12799ej6v0ds 7. package drawings detail of lead end m 18 9 16 s s a b h k m l p j i g c e f n d item b c i 16-pin plastic sop (7.62 mm (300)) a d e f g h j p millimeters 1.27 (t.p.) 0.78 max. 5.6 0.2 10.2 0.2 0.1 0.1 0.42 1.65 0.15 7.7 0.3 1.55 + 0.08 ? 0.07 1.1 0.2 3 + 7 ? 3 note each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. m l n 0.12 0.6 0.2 0.10 k 0.22 + 0.08 ? 0.07 p16gm-50-300b-6
pd6376 16 data sheet s12799ej6v0ds 8. recommended soldering conditions the following conditions must be met when performing soldering for the pd6376. for more detailed information, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than the recommended conditions, please consult with an nec sales representative. surface mount type soldering conditions pd6376gs: 16-pin plastic sop 7.62 mm (300) soldering process soldering conditions symbol infrared reflow peak package temperature: 230 c, time: 30 seconds max. (at 210 c or higher), ir30-00-1 count: once vps peak package temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp-15-00-1 count: once pin partial heating pin temperature: 300 c or less, time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for pin partial heating).
pd6376 17 data sheet s12799ej6v0ds [memo]
pd6376 18 data sheet s12799ej6v0ds [memo]
pd6376 19 data sheet s12799ej6v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd6376 m8e 00. 4 the information in this document is current as of may, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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